Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory

Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara. Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory. J. Solid-State Circuits, 29(4):454-460, April 1994. [doi]

Abstract

Abstract is missing.