Low-ESL (<1 pH @ 8.5 GHz) Multi-Terminal Si Capacitor Embedded in 3D Functional Interposer for Power Delivery Network

Kyosuke Kobinata, Tatsuya Funaki, Yoshiaki Satake, Hitoshi Matsuno, Seiji Hidaka, Shunsuke Abe, Hiroyuki Ito, Chih-Cheng Hsiao, Sheng-Yi Li, Young-Suk Kim, Takayuki Ohba. Low-ESL (<1 pH @ 8.5 GHz) Multi-Terminal Si Capacitor Embedded in 3D Functional Interposer for Power Delivery Network. In IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022. pages 385-386, IEEE, 2022. [doi]

Authors

Kyosuke Kobinata

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Tatsuya Funaki

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Yoshiaki Satake

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Hitoshi Matsuno

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Seiji Hidaka

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Shunsuke Abe

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Hiroyuki Ito

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Chih-Cheng Hsiao

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Sheng-Yi Li

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Young-Suk Kim

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Takayuki Ohba

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