Parallelized Hardware Rough Set Processor Architecture in FPGA for Core Calculation in Big Datasets

Maciej Kopczynski, Tomasz Grzes. Parallelized Hardware Rough Set Processor Architecture in FPGA for Core Calculation in Big Datasets. In 16th International Conference on Control, Automation, Robotics and Vision, ICARCV 2020, Shenzhen, China, December 13-15, 2020. pages 1098-1103, IEEE, 2020. [doi]

Abstract

Abstract is missing.