Packet Processing Architecture With Off-Chip LLC Using Interleaved 3D-Stacked DRAM - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki. Packet Processing Architecture With Off-Chip LLC Using Interleaved 3D-Stacked DRAM. In 20th IEEE International Conference on High Performance Switching and Routing, HPSR 2019, Xi'an, China, May 26-29, 2019. pages 1-6, IEEE, 2019. [doi]

This author has not been identified. Look up 'Tomohiro Korikawa' in GoogleThis author has not been identified. Look up 'Akio Kawabata' in GoogleThis author has not been identified. Look up 'Fujun He' in GoogleThis author has not been identified. Look up 'Eiji Oki' in Google

runs on WebDSL