Packet Processing Architecture With Off-Chip LLC Using Interleaved 3D-Stacked DRAM

Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki. Packet Processing Architecture With Off-Chip LLC Using Interleaved 3D-Stacked DRAM. In 20th IEEE International Conference on High Performance Switching and Routing, HPSR 2019, Xi'an, China, May 26-29, 2019. pages 1-6, IEEE, 2019. [doi]

@inproceedings{KorikawaKHO19-0,
  title = {Packet Processing Architecture With Off-Chip LLC Using Interleaved 3D-Stacked DRAM},
  author = {Tomohiro Korikawa and Akio Kawabata and Fujun He and Eiji Oki},
  year = {2019},
  doi = {10.1109/HPSR.2019.8807993},
  url = {https://doi.org/10.1109/HPSR.2019.8807993},
  researchr = {https://researchr.org/publication/KorikawaKHO19-0},
  cites = {0},
  citedby = {0},
  pages = {1-6},
  booktitle = {20th IEEE International Conference on High Performance Switching and Routing, HPSR 2019, Xi'an, China, May 26-29, 2019},
  publisher = {IEEE},
  isbn = {978-1-7281-1686-0},
}