A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a + 27.1 dBm WCDMA CMOS Power Amplifier

Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka. A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a + 27.1 dBm WCDMA CMOS Power Amplifier. J. Solid-State Circuits, 47(12):2964-2973, 2012. [doi]

@article{KousaiOYKN12,
  title = {A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a + 27.1 dBm WCDMA CMOS Power Amplifier},
  author = {Shouhei Kousai and Kohei Onizuka and Takashi Yamaguchi and Yasuhiko Kuriyama and Masami Nagaoka},
  year = {2012},
  doi = {10.1109/JSSC.2012.2217833},
  url = {http://dx.doi.org/10.1109/JSSC.2012.2217833},
  researchr = {https://researchr.org/publication/KousaiOYKN12},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {47},
  number = {12},
  pages = {2964-2973},
}