A prototype VLSI chip architecture for JPEG image compression

Mario Kovac, N. Ranganathan, Martin Zagar. A prototype VLSI chip architecture for JPEG image compression. In 1995 European Design and Test Conference, ED&TC 1995, Paris, France, March 6-9, 1995. pages 2-6, IEEE Computer Society, 1995. [doi]

Authors

Mario Kovac

This author has not been identified. Look up 'Mario Kovac' in Google

N. Ranganathan

This author has not been identified. Look up 'N. Ranganathan' in Google

Martin Zagar

This author has not been identified. Look up 'Martin Zagar' in Google