A prototype VLSI chip architecture for JPEG image compression - researchr publication

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Mario Kovac, N. Ranganathan, Martin Zagar. A prototype VLSI chip architecture for JPEG image compression. In 1995 European Design and Test Conference, ED&TC 1995, Paris, France, March 6-9, 1995. pages 2-6, IEEE Computer Society, 1995. [doi]

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