Mario Kovac, N. Ranganathan, Martin Zagar. A prototype VLSI chip architecture for JPEG image compression. In 1995 European Design and Test Conference, ED&TC 1995, Paris, France, March 6-9, 1995. pages 2-6, IEEE Computer Society, 1995. [doi]
@inproceedings{KovacRZ95,
title = {A prototype VLSI chip architecture for JPEG image compression},
author = {Mario Kovac and N. Ranganathan and Martin Zagar},
year = {1995},
doi = {10.1109/EDTC.1995.470428},
url = {http://doi.ieeecomputersociety.org/10.1109/EDTC.1995.470428},
researchr = {https://researchr.org/publication/KovacRZ95},
cites = {0},
citedby = {0},
pages = {2-6},
booktitle = {1995 European Design and Test Conference, ED&TC 1995, Paris, France, March 6-9, 1995},
publisher = {IEEE Computer Society},
isbn = {0-8186-7039-8},
}