Combine and top down block placement algorithm for hierarchical logic VLSI layout - researchr publication authors

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Tokinori Kozawa, Chihei Miura, Hidekazu Terai. Combine and top down block placement algorithm for hierarchical logic VLSI layout. In Patricia H. Lambert, Hillel Ofek, Lawrence A. O'Neill, Pat O. Pistilli, Paul Losleben, J. D. Nash, Dennis W. Shaklee, Bryan T. Preas, Harvey N. Lerman, editors, Proceedings of the 21st Design Automation Conference, DAC '84, Albuquerque, New Mexico, June 25-27, 1984. pages 667-669, ACM/IEEE, 1984. [doi]

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