Tokinori Kozawa, Chihei Miura, Hidekazu Terai. Combine and top down block placement algorithm for hierarchical logic VLSI layout. In Patricia H. Lambert, Hillel Ofek, Lawrence A. O'Neill, Pat O. Pistilli, Paul Losleben, J. D. Nash, Dennis W. Shaklee, Bryan T. Preas, Harvey N. Lerman, editors, Proceedings of the 21st Design Automation Conference, DAC '84, Albuquerque, New Mexico, June 25-27, 1984. pages 667-669, ACM/IEEE, 1984. [doi]
@inproceedings{KozawaMT84,
title = {Combine and top down block placement algorithm for hierarchical logic VLSI layout},
author = {Tokinori Kozawa and Chihei Miura and Hidekazu Terai},
year = {1984},
url = {http://dl.acm.org/citation.cfm?id=800876},
researchr = {https://researchr.org/publication/KozawaMT84},
cites = {0},
citedby = {0},
pages = {667-669},
booktitle = {Proceedings of the 21st Design Automation Conference, DAC '84, Albuquerque, New Mexico, June 25-27, 1984},
editor = {Patricia H. Lambert and Hillel Ofek and Lawrence A. O'Neill and Pat O. Pistilli and Paul Losleben and J. D. Nash and Dennis W. Shaklee and Bryan T. Preas and Harvey N. Lerman},
publisher = {ACM/IEEE},
isbn = {0-8186-0542-1},
}