Design of Dependable Hardware: What BIST is most Efficient?

Andrzej Krasniewski. Design of Dependable Hardware: What BIST is most Efficient?. In Andrzej Hlawiczka, João Gabriel Silva, Luca Simoncini, editors, Dependable Computing - EDCC-2, Second European Dependable Computing Conference, Taormina, Italy, October 2-4, 1996, Proceedings. Volume 1150 of Lecture Notes in Computer Science, pages 233-245, Springer, 1996.

Abstract

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