A single chip, pipelined, cascadable, multichannel, signal processor - researchr publication authors

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S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta. A single chip, pipelined, cascadable, multichannel, signal processor. In 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India. pages 150-155, IEEE Computer Society, 1995. [doi]

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