Kyle Kuan, Tosiron Adegbija. Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. IEEE Trans. on CAD of Integrated Circuits and Systems, 39(6):1328-1339, 2020. [doi]
@article{KuanA20,
title = {Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design},
author = {Kyle Kuan and Tosiron Adegbija},
year = {2020},
doi = {10.1109/TCAD.2019.2912920},
url = {https://doi.org/10.1109/TCAD.2019.2912920},
researchr = {https://researchr.org/publication/KuanA20},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {39},
number = {6},
pages = {1328-1339},
}