FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor - researchr publication authors

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Vivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta. FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor. In 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, VLSID 2023, Hyderabad, India, January 8-12, 2023. pages 1-6, IEEE, 2023. [doi]

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