Vivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta. FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor. In 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, VLSID 2023, Hyderabad, India, January 8-12, 2023. pages 1-6, IEEE, 2023. [doi]
@inproceedings{KumarPDD23,
title = {FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor},
author = {Vivek Kumar and Jyoti Patel and Arnab Datta and Sudeb Dasgupta},
year = {2023},
doi = {10.1109/VLSID57277.2023.00067},
url = {https://doi.org/10.1109/VLSID57277.2023.00067},
researchr = {https://researchr.org/publication/KumarPDD23},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, VLSID 2023, Hyderabad, India, January 8-12, 2023},
publisher = {IEEE},
isbn = {979-8-3503-4678-7},
}