Table of Contents

• A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS ProcessRupesh D. Kadhao, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Devesh Dwivedi. 1-6 [doi]
• A Low Noise Bandgap Reference with 0.89 V Vref, 0.88 μVrms noise and 80 dB of PSRRSowmyashree S, Hitesh Shrimali. 1-6 [doi]
• WIB-SAR: Write Intensity Based Selective Address RemappingN. S. Aswathy, Deep Bhuinya, Hemangee K. Kapoor. 1-6 [doi]
• Live & Seamless Firmware Upgrade in Real Time Control SystemsSira Rao, Baskaran Chidambaram, Prasanth V., Karthik Rajakumar, Pramod Prabhakara, Praveen Ravichandran, Shailesh Ghotgalkar, Ashish Vanjari, Mihir Mody. 1-5 [doi]
• Efficient 3D Modeling Methodology for High-Speed ChannelsSivalingam Thirubalan, Suresh Kumar Kopparti, Desmond Tan Hai Peng. 1-6 [doi]
• FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet TransistorVivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta. 1-6 [doi]
• GRILAPE: Graph Representation Inductive Learning-based Average Power Estimation for Frontend ASIC RTL DesignsRakesh M. B., Pabitra Das, Sai Pranav K. R, Amit Acharyya. 1-6 [doi]
• Delay-Aware Control for Autonomous SystemsSumana Ghosh. 1-6 [doi]
• Design of Energy Efficient and Low Delay Posit MultiplierK. Lakshmi BhanuPrakash Reddy, Haripriya R. S, Keerthija Puli, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi. 1-6 [doi]
• InsectEye: An Intelligent Trap for Insect Biodiversity MonitoringEric Homan, Codey Mathis, Chonghan Lee, Harland M. Patch, Christina M. Grozinger, Vijay Narayanan. 1-6 [doi]
• Translation of Array Expressions for in-Memory Computation on Memristive CrossbarSumanta Pyne. 1-6 [doi]
• A 2.25 GHz PLL with 0.05-2 MHz Inloop Phase Modulation and -70 dBc Reference Spur for Telemetry ApplicationsSnigdha Jakkoju, Deepthi J. Bandarupalli, Anil Srikanth, Saji Thomas, Saurabh Saxena. 1-5 [doi]
• Hardware implementation of Ring-LWE lattice cryptography with BCH and Gray coding based error correctionSomnath Mondal, Sachin Patkar, T. K. Pal. 1-6 [doi]
• Maximum Power Point Tracking using Buck-Boost converter for EH-PMICSujata Kotabagi, Raghavendra Nayak, Sachin Dalabanjan, Vineet P. N, Priyanka L. Patil, Sameer Hemadri. 1-6 [doi]
• Machine Learning-based model for Single Event Upset Current Prediction in 14nm FinFETsVibhu, Sparsh Mittal, Vivek Kumar. 1-6 [doi]
• Hardware Architecture and FPGA Implementation of Low Latency Turbo Encoder for Deep-Space Communication SystemsMeghvern Pathak, Rahul Shrestha. 1-6 [doi]
• Lightweight Approximate Multiplier with Improved Accuracy in FPGA for Error Resilient ApplicationApurba Prasad Padhy, Bishnu Prasad Das. 7-12 [doi]
• DRRA-based Reconfigurable Architecture for Mixed-Radix FFTReeshita Kallapu, Dimitrios Stathis 0001, Srinivas Boppu, Ahmed Hemani. 25-30 [doi]
• Design of a Multi-Core Compatible Linux Bootable 64-bit Out-of-Order RISC-V Processor CoreSajin S, Shubham Sunil Garag, Anuj Phegade, Deepshikha Gusain, Kuruvilla Varghese. 42-47 [doi]
• Voltage Boosted Schmitt Trigger Sense Amplifier (VBSTSA) With Improved Offset And Reaction Time For High Speed SRAMsGaurav Saraswat, Anuj Parashar. 48-52 [doi]
• Radiation Hardened CMOS Programmable Bias Generator for Space Applications at 180nmAshutosh Yadav, Anand Bulusu, Surinder Singh, Sudeb Dasgupta. 59-62 [doi]
• A low-power resistive tail dynamic comparator with self-shut mechanismSanjoy Kumar Dey, Mukul Sarkar, Shouribrata Chatterjee. 63-68 [doi]
• A Sense Amplifier Based Bulk Built-In Current Sensor for Detecting Laser-Induced CurrentsDebjit Batabyal, Sandeep Kumar Singh, Rajnish Kumar Mishra, Anuj Grover. 69-74 [doi]
• Unifying Intrinsically-Operated Physically Unclonable Function and Random Number Generation in Analog Circuits: A Case Study on Successive Approximation ADCAhish Shylendra, Swarup Bhunia, Amit Ranjan Trivedi. 75-80 [doi]
• Programmable Delay Line With Inherent Duty Cycle CorrectionSiva Charan Nimmagadda, Hari Bilash Dubey. 81-86 [doi]
• Ultra-Low Power Non-Uniform SAR ADC based ECG detector for Early Detection of Cardiovascular DiseasesAditya Ramkumar, Anshul Verma, Bishnu Prasad Das. 92-97 [doi]
• Design Challenges and Techniques for 5nm FinFET CMOS Analog/Mixed-Signal CircuitsSaurabh Goyal, Sanjay Kumar Wadhwa, Divya Tripathi, Gaurav Agrawal, Krishna Thakur, Deependra Kumar Jain, Alvin L.-S. Loke, Atul Kumar, Manish Kumar Upadhyay, Bhawna, Sanjoy Kumar Dey. 98-103 [doi]
• Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space ApplicationMohd Sakib Ansari S, Kavitha S, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma. 104-108 [doi]
• Design and Analysis of Multibit Multiply and Accumulate (MAC) unit: An Analog In-Memory Computing ApproachSwetha Ananthanarayanan, Bhupendra Singh Reniwal, Abhishek Upadhyay. 109-114 [doi]
• A Common Mode Insensitive Process Tolerant Sense Amplifier Design for In Memory Compute Applications in 65nm LSTP TechnologyBelal Iqbal, Anuj Grover, Harsh Rawat. 121-126 [doi]
• Supply Noise and Peak Current Reduction in High-Speed Output DriversDharmaray Nedalgi, Lavanya M. N, Saroja V. Siddamal. 127-132 [doi]
• An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing ArchitectureNoopur Srivastava, Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal. 133-138 [doi]
• Memristor-based High Speed and Area Efficient Comparators in IMPLY LogicNandit Kaushik, B. Srinivasu. 139-144 [doi]
• Design of Hardware Efficient Approximate DCT ArchitectureVishwajeet S. B, Vaibhavi Solanki, Anand D. Darji. 145-150 [doi]
• Surmounting Challenges in the Design of Low Power Real Time Clock IP for Advanced FinFET Technology NodesKrishnan Sukumar, Santosh Vodnala, Ravindra Ayyagari, Animesh Jain, Thanapandi Ganesan, Rajesh R. 157-162 [doi]
• Dynamic Keeper for 1R1W 8T-SRAM to Enable Read Operation at 150c till 0.5v in 5nm FinFETVinay Kumar, Vijay Sahu, Ambar Khanda, Sudhir Kumar. 163-168 [doi]
• ASPIRE: An Intermediate Representation for Abstract Security PoliciesPadmaja Bhamidipati, Ranga Vemuri. 175-180 [doi]
• MLTDRC: Machine Learning Driven Faster Timing Design Rule Check ConvergenceSantanu Kundu, Chetan Suryakant Padharia, Ravi Sankar Kerla. 181-186 [doi]
• Transport-Free Placement of Mixers for Realizing Bioprotocol on Programmable Microfluidic DevicesMasataka Hirai, Debraj Kundu, Shigeru Yamashita, Sudip Roy 0001, Hiroyuki Tomiyama. 193-198 [doi]
• ISP: An Improved Slicing Pair Code for Skewed Slicing FloorplanBiswojit Nayak, B. N. Bhramar Ray. 205-210 [doi]
• Efficient MBIST Area and Test Time Estimator Using Machine Learning TechniqueDarakshan Jamal, Ratheesh Veetil. 223-228 [doi]
• A Novel AI Based Approach for Performance validationKahkeshan Naz, Rohit Jindal, Sai Boothkuri. 229-233 [doi]
• Signal Agnostic Scalable Scan Wrapper DesignHanumantharaya H, Ratheesh T. Veetil, Anvesh Gadi. 234-239 [doi]
• Mutation Analysis and Model Checking Guided Test Generation for SoC Run-Time MonitorsSuriya Srinivasan, Ranga Vemuri. 240-245 [doi]
• Extending Action Recognition in the Compressed DomainSamuel Abrams, Vijaykrishnan Narayanan. 246-251 [doi]
• Design and Analysis of Posit Quire Processing Engine for Neural Network ApplicationsPranose J. Edavoor, Aneesh Raveendran, David Selvakumar, Vivian Desalphine, Shankar G. Dharani, Gopal Raut. 252-257 [doi]
• Fast and Robust Sense Amplifier for Digital In Memory ComputingKailash Prasad, Ayush Srivastava, Nistha Baruah, Joycee Mekie. 258-263 [doi]
• MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable TilesNoble G, Nalesh S, S. Kala. 264-269 [doi]
• A Portable Ultra-low-cost Multi-Gas Sensing System-on-Module for Wireless Air Quality Monitoring NetworkAnamika Sharma, Sachin Divekar, Rajesh Zele. 270-273 [doi]
• FPGA based Smart and Sustainable AgricultureShyam Peraka, SK Irfan Ali, Durga Vasu Mogili, Ashok Kumar Palivela, Sudheer Reddy, Jyotsna Bavisetti, Dhanush Reddy Y. 274-278 [doi]
• SV Based Fast & Accurate Verification Methodology for CTLE Adaptation AlgorithmAbhishek Jadhav, Varsha Bhide, T. N. V. Raghuram, Tapas Nandy. 279-283 [doi]
• A 16Gbps 3rd Order CTLE Design for Serial Links with High Channel Loss in 16nm FinFETThota Pranay Kumar, Siva Kumar Rapina, Bheema Rao Nistala. 284-289 [doi]
• Enhanced Performance Parameters of Magnetic Tunnel Junction with Composite Dielectric BarrierReshma Sinha, Jasdeep Kaur. 290-294 [doi]
• Automatic Implementation and Evaluation of Error-Correcting Codes for Quantum Computing: An Open-Source Framework for Quantum Error CorrectionThomas Grurl, Christoph Pichler, Jürgen Fuß, Robert Wille. 301-306 [doi]
• Implementation of Probabilistic Bits (Pbits) using Low Barrier Magnets: Investigation and AnalysisAmina Haroon, Ram Krishna Ghosh, Sneh Saurabh. 307-312 [doi]
• Post Silicon Validation for I2C (SMBUS) PeripheralSwati Shilaskar, Anup Behare, Ketki Sonawane, Shripad Bhatlawande. 313-318 [doi]
• Efficient FPGA Implementations of Lifting based DWT using Partial ReconfigurationM. Mohamed Asan Basiri, PVSR Bharadwaja. 319-324 [doi]
• Accelerating Defect Simulation in Analog and Mixed-Signal Circuits by Parallel Defect InjectionSayandeep Sanyal, Mayukh Bhattacharya, Pallab Dasgupta, Amit Patra. 325-330 [doi]
• Mutual Information based Efficient Spike Encoding on FPGAOmkareshwar Gundoji, Dighanchal Banerjee, Sounak Dey, Arpan Pal. 331-336 [doi]
• SANNA: Secure Acceleration of Neural Network ApplicationsAkash Poptani, Abhishek Mittal, Rishit Saiya, Rajshekar Kalayappan, Sandeep Chandran. 337-342 [doi]
• The Acceleration of OPUS Codec Using Processor - FPGA Co-processingSunny Bezawada, Battu Prakash Reddy. 343-347 [doi]
• A 105-525MHz Integer-N Phase-Locked Loop in Indigenous SCL 180nm CMOSShivam Nigam, Mukund Murali, Hari Shanker Gupta, Saurabh Saxena. 348-352 [doi]
• Evaluating the Impact of Transition Delay Faults in GPUsJosie E. Rodriguez Condia, Matteo Sonza Reorda. 353-358 [doi]
• An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design MethodologyDinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu. 359-364 [doi]
• Reliability Enhancement of Hardware Trojan Detection using Histogram Augmentation TechniqueVaishnavi Sankar, Balachander Sathianarayanan, Nirmala Devi Manickam, M. Jayakumar 0001. 365-370 [doi]
• DARK-Adders: Digital Hardware Trojan Attack on Block-based Approximate AddersVishesh Mishra, Neelofar Hassan, Akshay Mehta, Urbi Chatterjee. 371-376 [doi]
• True Random Number Generator based on Voltage-Gated Spintronic structureAlisha P. B, Tripti S. Warrier. 377-382 [doi]
• A Novel Approach for Assisting Blind People Using a Smart Wearable DeviceShyam Peraka, SK Irfan Ali, Reddy Sudheer, Pilli Praveen Kumar, Goutham Kondala, Dimple Samal. 383-388 [doi]
• Word-Level Structure Identification In FPGA Designs Using Cell Proximity InformationAparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri. 389-394 [doi]
• Analysis and Design of Low Phase Noise 20 GHz VCO for Frequency Modulated Continuous Wave Chirp Synthesizers in mmWave RadarsHarikrishna Kambham, Srayan Sankar Chatterjee, Adithya Sunil Edakkadan, Abhishek Srivastava 0002. 395-400 [doi]
• An mmWave Frequency Range Multi-Modulus Programmable Divider for FMCW Radar ApplicationsSresthavadhani Mantha, Adithya Sunil Edakkadan, Arpit Sahni, Abhishek Srivastava 0002. 407-412 [doi]