Hardware Architecture and FPGA Implementation of Low Latency Turbo Encoder for Deep-Space Communication Systems - researchr publication

researchr

You are not signed in
Sign in
Sign up

Meghvern Pathak, Rahul Shrestha. Hardware Architecture and FPGA Implementation of Low Latency Turbo Encoder for Deep-Space Communication Systems. In 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, VLSID 2023, Hyderabad, India, January 8-12, 2023. pages 1-6, IEEE, 2023. [doi]

Abstract is missing.

runs on WebDSL