A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFET - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Vinay Kumar, Nikhil Puri, Sudhir Kumar, Sumit Srivastav. A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFET. In 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, VLSID 2017, Hyderabad, India, January 7-11, 2017. pages 269-274, IEEE Computer Society, 2017. [doi]

This author has not been identified. Look up 'Vinay Kumar' in GoogleThis author has not been identified. Look up 'Nikhil Puri' in GoogleThis author has not been identified. Look up 'Sudhir Kumar' in GoogleThis author has not been identified. Look up 'Sumit Srivastav' in Google

runs on WebDSL