TSV and DFT cost aware circuit partitioning for 3D-SOCs - researchr publication authors

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Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker. TSV and DFT cost aware circuit partitioning for 3D-SOCs. In Keith A. Bowman, Kamesh V. Gadepally, Pallab Chatterjee, Mark M. Budnik, Lalitha Immaneni, editors, Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012. pages 21-26, IEEE, 2012. [doi]

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