A comparative study on formal verification techniques to verify large integer multiplier circuits

Jitendra Kumar, Asutosh Srivastava, Masahiro Fujita 0004. A comparative study on formal verification techniques to verify large integer multiplier circuits. Integration, 107:102606, 2026. [doi]

@article{KumarSF26,
  title = {A comparative study on formal verification techniques to verify large integer multiplier circuits},
  author = {Jitendra Kumar and Asutosh Srivastava and Masahiro Fujita 0004},
  year = {2026},
  doi = {10.1016/j.vlsi.2025.102606},
  url = {https://doi.org/10.1016/j.vlsi.2025.102606},
  researchr = {https://researchr.org/publication/KumarSF26},
  cites = {0},
  citedby = {0},
  journal = {Integration},
  volume = {107},
  pages = {102606},
}