M. Jagadesh Kumar, Vivek Venkataraman, Susheel Nawal. Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation. In 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India. pages 189-194, IEEE Computer Society, 2007. [doi]
@inproceedings{KumarVN07,
title = {Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation},
author = {M. Jagadesh Kumar and Vivek Venkataraman and Susheel Nawal},
year = {2007},
doi = {10.1109/VLSID.2007.38},
url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.38},
researchr = {https://researchr.org/publication/KumarVN07},
cites = {0},
citedby = {0},
pages = {189-194},
booktitle = {20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India},
publisher = {IEEE Computer Society},
isbn = {0-7695-2502-4},
}