The following publications are possibly variants of this publication:
- A high throughput VLSI design with hybrid memory architecture for H.264/AVC CABAC decoderYuan-Hsin Liao, Gwo-Long Li, Tian-Sheuan Chang. iscas 2010: 2007-2010 [doi]
- A Hardware Architecture of CABAC Encoding and Decoding with Dynamic Pipeline for H.264/AVCLingfeng Li, Yang Song, Shen Li, Takeshi Ikenaga, Satoshi Goto. vlsisp, 50(1):81-95, 2008. [doi]
- A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC DecoderYuan-Hsin Liao, Gwo-Long Li, Tian-Sheuan Chang. tcsv, 22(2):272-281, 2012. [doi]