An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions

Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura. An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions. In Peter M. Athanas, René Cumplido, Claudia Feregrino, Ron Sass, editors, International Conference on ReConFigurable Computing and FPGAs, ReConFig 2016, Cancun, Mexico, November 30 - Dec. 2, 2016. pages 1-6, IEEE, 2016. [doi]

@inproceedings{KusanoIAM16,
  title = {An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions},
  author = {Hotaka Kusano and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
  year = {2016},
  doi = {10.1109/ReConFig.2016.7857153},
  url = {http://dx.doi.org/10.1109/ReConFig.2016.7857153},
  researchr = {https://researchr.org/publication/KusanoIAM16},
  cites = {0},
  citedby = {0},
  pages = {1-6},
  booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig 2016, Cancun, Mexico, November 30 - Dec. 2, 2016},
  editor = {Peter M. Athanas and René Cumplido and Claudia Feregrino and Ron Sass},
  publisher = {IEEE},
  isbn = {978-1-5090-3707-0},
}