Abstract is missing.
- Keynote 2 - FPGAs in the datacenter - A software viewSkip Booth. 1 [doi]
- ARM+FPGA platform to manage solid-state-smart transformer in smart grid applicationN. Nila-Olmedo, F. Mendoza-Mondragon, A. Espinosa-Calderon, Moreno. 1-6 [doi]
- The portable open-source IP core and utility library PoCThomas B. Preuser, Martin Zabel, Patrick Lehmann, Rainer G. Spallek. 1-6 [doi]
- Towards FPGA-assisted spark: An SVM training acceleration case studySam M. H. Ho, Maolin Wang, Ho-Cheung Ng, Hayden Kwok-Hay So. 1-6 [doi]
- An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversionsHotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura. 1-6 [doi]
- FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecastingKentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura. 1-6 [doi]
- Hybrid energy-aware reconfiguration management on Xilinx Zynq SoCsAndreas Becher, Jutta Pirkl, Achim Herrmann, Jürgen Teich, Stefan Wildermann. 1-7 [doi]
- An FPGA-based design for joint control and monitoring of permanent magnet synchronous motorsPaul Rogers, Rajesh Kavasseri, Scott C. Smith. 1-6 [doi]
- 1 Tb/s anti-replay protection with 20-port on-chip RAM memory in FPGAsBenjamin R. Buhrow, William J. Goetzinger, Barry K. Gilbert. 1-8 [doi]
- High-level synthesis of a genomic database search engineRasha Karakchi, Jordan A. Bradshaw, Jason D. Bakos. 1-6 [doi]
- High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platformHo-Cheung Ng, Maolin Wang, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Sam M. H. Ho, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So. 1-6 [doi]
- Adaptive single-event effect mitigation for dependable processing systemsRobért Glein, Florian Rittner, Albert Heuberger. 1-8 [doi]
- Overloaded CDMA interconnect for Network-on-Chip (OCNoC)Khaled E. Ahmed, Mohamed R. Rizk, Mohammed M. Farag. 1-7 [doi]
- Efficient deep neural network acceleration through FPGA-based batch processingThorbjorn Posewsky, Daniel Ziener. 1-8 [doi]
- Dual fixed-point CORDIC processor: Architecture and FPGA implementationAndres Jacoby, Daniel Llamocca. 1-8 [doi]
- Keynote 1 - Growing the ReConFig community through python, zynq and hardware overlaysGraham Schelle. 1 [doi]
- Automating structured matrix-matrix multiplication for stream processingThaddeus Koehn, Peter Athanas. 1-6 [doi]
- Design and implementation of a constant-time FPGA accelerator for fast elliptic curve cryptographyAtil U. Ay, Erdinç Öztürk, Francisco Rodríguez-Henríquez, Erkay Savas. 1-8 [doi]
- An effective probability distribution SAT solver on reconfigurable hardwareAli Asgar Sohanghpurwala, Peter M. Athanas. 1-6 [doi]
- Real-time image distortion correction: Analysis and evaluation of FPGA-compatible algorithmsPaolo Di Febbo, Stefano Mattoccia, Carlo Dal Mutto. 1-6 [doi]
- Hobbit - Smaller but faster than a dwarf: Revisiting lightweight SHA-3 FPGA implementationsBernhard Jungk, Marc Stöttinger. 1-7 [doi]
- A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoCPaolo Meloni, Gianfranco Deriu, Francesco Conti 0001, Igor Loi, Luigi Raffo, Luca Benini. 1-8 [doi]
- Dataflow optimization for programmable embedded image preprocessing acceleratorsTobias Lieske, Marc Reichenbach, Burkhard Ringlein, Dietmar Fey. 1-8 [doi]
- A configurable architecture for the generalized hough transform applied to the analysis of huge aerial images and to traffic sign detectionGundolf Kiefer, Matthias Vahl, Julian Sarcher, Michael Schaeferling. 1-7 [doi]
- ReOrder: Runtime datapath generation for high-throughput multi-stream processingAndreas Becher, Stefan Wildermann, Moritz Mühlenthaler, Jürgen Teich. 1-8 [doi]
- An FPGA implementation of a long short-term memory neural networkJoão Canas Ferreira, Jose Fonseca. 1-8 [doi]
- Area-driven partial reconfiguration for SEU mitigation on SRAM-based FPGAsMichail S. Vavouras, Christos-Savvas Bouganis. 1-6 [doi]
- A novel and efficient method to initialize FPGA embedded memory content in asymptotically constant timeMatej Bartik, Sven Ubik, Pavel Kubalík. 1-6 [doi]
- A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contestsFarnoud Farahmand, Ekawat Homsirikamol, Kris Gaj. 1-7 [doi]
- Enabling dynamic and partial reconfiguration in Xilinx SDSoCTobias Kalb, Diana Göhringer. 1-7 [doi]
- FPGA implementation of optimized XBM specifications by transformation for AFSMsKledermon Garcia, Duarte L. Oliveira, Roberto d'Amore, Lester A. Faria, Joao Luis V. Oliveira. 1-6 [doi]
- FPGA-based encrypted network traffic identification at 100 Gbit/sMario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara. 1-6 [doi]
- FPGA debugging by a device start and stop approachHabib ul Hasan Khan, Diana Göhringer. 1-6 [doi]
- Automatic framework to generate reconfigurable accelerators for option pricing applicationsPham Nam Khanh, Khin Mi Mi Aung, Akash Kumar 0001. 1-8 [doi]
- Thread shadowing: On the effectiveness of error detection at the hardware thread levelSebastian Meisner, Marco Platzner. 1-8 [doi]
- Coarse grain reconfiguration: Power estimation and management flow for hybrid gated systemsTiziana Fanni, Luigi Raffo. 1-4 [doi]
- Detection and Isolation of permanent faults in FPGAs with remote accessFlorian Rittner, Robért Glein, Albert Heuberger. 1-4 [doi]
- Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platformsErnst Joachim Houtgast, Vlad Mihai Sima, Giacomo Marchiori, Koen Bertels, Zaid Al-Ars. 1-8 [doi]
- Solving large systems of linear equations over GF(2) on FPGAsWen Wang, Jakub Szefer, Ruben Niederhagen. 1-7 [doi]
- A scalable latency-insensitive architecture for FPGA-accelerated semi-global matching in stereo vision applicationsJaco Hofmann, Jens Korinth, Andreas Koch 0001. 1-8 [doi]
- Robust bitstream protection in FPGA-based systems through low-overhead obfuscationRobert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor, Swarup Bhunia. 1-8 [doi]
- Survey on and re-evaluation of wide adder architectures on FPGAsThomas B. Preußer, Markus Krause. 1-6 [doi]
- The R2-D2 toolchain - Automated porting of safety-critical applications to FPGAsSteffen Vaas, Marc Reichenbach, Ulrich Margull, Dietmar Fey. 1-7 [doi]
- Breeze computing: A just in time (JIT) approach for virtualizing FPGAs in the cloudSen Ma, David Andrews, Shanyuan Gao, Jaime Cummins. 1-6 [doi]
- REoN: A protocol for reliable software-defined FPGA partial reconfiguration over networkVaibhawa Mishra, Qianqiao Chen, Georgios Zervas. 1-7 [doi]
- Packing a modern Xilinx FPGA using RapidSmithTravis Haroldsen, Brent E. Nelson, Brad L. Hutchings. 1-6 [doi]
- RePaBit: Automated generation of relocatable partial bitstreams for Xilinx Zynq FPGAsJens Rettkowski, Konstantin Friesen, Diana Göhringer. 1-8 [doi]
- Hardware-accelerated pose estimation for embedded systems using Vivado HLSJan Moritz Joseph, Tobias Winker, Kristian Ehlers, Christopher Blochwitz, Thilo Pionteck. 1-7 [doi]
- Design and implementation of hardware cache mechanism and NIC for column-oriented databasesAkihiko Hamada, Hiroki Matsutani. 1-6 [doi]
- Technical demonstration session: Software toolflow for FPGA bitstream obfuscationRobert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor, Swarup Bhunia. 1-2 [doi]
- Data-rate-aware FPGA-based acceleration framework for streaming applicationsSiavash Rezaei, Cesar-Alejandro Hernandez-Calderon, Saeed Mirzamohammadi, Eli Bozorgzadeh, Alexander V. Veidenbaum, Alex Nicolau, Michael J. Prather. 1-6 [doi]
- Optimal processor interface for CGRA-based accelerators implemented on FPGAsLukas Johannes Jung, Christian Hochberger. 1-7 [doi]
- A multi-functional memory unit with PLA-based reconfigurable decoderNobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen. 1-7 [doi]
- Reconfigurable computing for network function virtualization: A protocol independent switchQianqiao Chen, Vaibhawa Mishra, Georgios Zervas. 1-6 [doi]
- Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applicationsJose Fernando Zazo, Sergio López-Buedo, Gustavo Sutter, Javier Aracil. 1-6 [doi]