An experimental 295 MHz CMOS 4K/spl times/256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers

Natsuki Kushiyama, Charles Tan, Richard Clark, Jane Lin, Fred Perner, Lisa Martin, Mark Leonard, Gene Coussens, Kit Cham. An experimental 295 MHz CMOS 4K/spl times/256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers. J. Solid-State Circuits, 30(11):1286-1290, November 1995. [doi]

@article{KushiyamaTCLPMLCC95,
  title = {An experimental 295 MHz CMOS 4K/spl times/256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers},
  author = {Natsuki Kushiyama and Charles Tan and Richard Clark and Jane Lin and Fred Perner and Lisa Martin and Mark Leonard and Gene Coussens and Kit Cham},
  year = {1995},
  month = {November},
  doi = {10.1109/4.475718},
  url = {https://doi.org/10.1109/4.475718},
  researchr = {https://researchr.org/publication/KushiyamaTCLPMLCC95},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {30},
  number = {11},
  pages = {1286-1290},
}