AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture

Kon-Woo Kwon, Sri Harsha Choday, Yusung Kim, Kaushik Roy. AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture. IEEE Trans. VLSI Syst., 22(4):712-720, 2014. [doi]

Abstract

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