Tzu-Yi Lai, Kuan-Hung Chen. On-Chip Memory Optimization of High Efficiency Accelerator for Deep Convolutional Neural Networks. In International SoC Design Conference, ISOCC 2018, Daegu, South Korea, November 12-15, 2018. pages 82-83, IEEE, 2018. [doi]
@inproceedings{LaiC18-4,
title = {On-Chip Memory Optimization of High Efficiency Accelerator for Deep Convolutional Neural Networks},
author = {Tzu-Yi Lai and Kuan-Hung Chen},
year = {2018},
doi = {10.1109/ISOCC.2018.8649945},
url = {https://doi.org/10.1109/ISOCC.2018.8649945},
researchr = {https://researchr.org/publication/LaiC18-4},
cites = {0},
citedby = {0},
pages = {82-83},
booktitle = {International SoC Design Conference, ISOCC 2018, Daegu, South Korea, November 12-15, 2018},
publisher = {IEEE},
isbn = {978-1-5386-7960-9},
}