A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform

Yeong-Kang Lai, Lien-Fei Chen, Yui-Chih Shih. A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform. IEEE Trans. Consumer Electronics, 55(2):400-407, 2009. [doi]

Authors

Yeong-Kang Lai

This author has not been identified. Look up 'Yeong-Kang Lai' in Google

Lien-Fei Chen

This author has not been identified. Look up 'Lien-Fei Chen' in Google

Yui-Chih Shih

This author has not been identified. Look up 'Yui-Chih Shih' in Google