The following publications are possibly variants of this publication:
- A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet TransformChien-Yu Chen, Zhong-Lan Yang, Tu-Chih Wang, Liang-Gee Chen. vlsisp, 28(3):151-163, 2001. [doi]
- VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet TransformPei-Yin Chen. ieicet, 87-A(1):275-279, 2004. [doi]
- VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applicationsJen-Shiun Chiang, Chih-Hsien Hsia, Hsin-Jung Chen, Te-Jung Lo. iscas 2005: 4554-4557 [doi]
- Efficient VLSI architecture for 2-D inverse discrete wavelet transformsChu Yu, Sao-Jie Chen. iscas 1999: 524-527 [doi]