A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform

Yeong-Kang Lai, Lien-Fei Chen, Yui-Chih Shih. A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform. IEEE Trans. Consumer Electronics, 55(2):400-407, 2009. [doi]

Abstract

Abstract is missing.