Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs

Jyh-Ting Lai, An-Yeu Wu, Chien-Hsiung Lee. Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. IEEE Trans. VLSI Syst., 15(2):236-240, 2007. [doi]

Authors

Jyh-Ting Lai

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An-Yeu Wu

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Chien-Hsiung Lee

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