Performance analysis of alternative adder cell structures using clocked and non-clocked logic styles at 45nm technology

T. Bhagya Laxmi, S. Rajendar, Y. Pandu Rangaiah. Performance analysis of alternative adder cell structures using clocked and non-clocked logic styles at 45nm technology. In 2014 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2014, Delhi, India, September 24-27, 2014. pages 620-623, IEEE, 2014. [doi]

Authors

T. Bhagya Laxmi

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S. Rajendar

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Y. Pandu Rangaiah

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