T. Bhagya Laxmi, S. Rajendar, Y. Pandu Rangaiah. Performance analysis of alternative adder cell structures using clocked and non-clocked logic styles at 45nm technology. In 2014 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2014, Delhi, India, September 24-27, 2014. pages 620-623, IEEE, 2014. [doi]
@inproceedings{LaxmiRR14,
title = {Performance analysis of alternative adder cell structures using clocked and non-clocked logic styles at 45nm technology},
author = {T. Bhagya Laxmi and S. Rajendar and Y. Pandu Rangaiah},
year = {2014},
doi = {10.1109/ICACCI.2014.6968445},
url = {http://dx.doi.org/10.1109/ICACCI.2014.6968445},
researchr = {https://researchr.org/publication/LaxmiRR14},
cites = {0},
citedby = {0},
pages = {620-623},
booktitle = {2014 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2014, Delhi, India, September 24-27, 2014},
publisher = {IEEE},
isbn = {978-1-4799-3078-4},
}