A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation

Hyunui Lee, Yusuke Asada, Masaya Miyahara, Akira Matsuzawa. A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation. IEICE Transactions, 96-A(2):422-433, 2013. [doi]

Abstract

Abstract is missing.