Electrical method to localize the high-resistance of nanoscale CoSi2 word-line for OTP memories

Ming-Yi Lee, T. Y. Chang, W.-F. Hsueh, L.-K. Kuo, D.-J. Lin, Y.-H. Chao, U. J. Tzeng, C. Y. Lu. Electrical method to localize the high-resistance of nanoscale CoSi2 word-line for OTP memories. In IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018. pages 6, IEEE, 2018. [doi]

@inproceedings{LeeCHKLCTL18,
  title = {Electrical method to localize the high-resistance of nanoscale CoSi2 word-line for OTP memories},
  author = {Ming-Yi Lee and T. Y. Chang and W.-F. Hsueh and L.-K. Kuo and D.-J. Lin and Y.-H. Chao and U. J. Tzeng and C. Y. Lu},
  year = {2018},
  doi = {10.1109/IRPS.2018.8353624},
  url = {https://doi.org/10.1109/IRPS.2018.8353624},
  researchr = {https://researchr.org/publication/LeeCHKLCTL18},
  cites = {0},
  citedby = {0},
  pages = {6},
  booktitle = {IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018},
  publisher = {IEEE},
  isbn = {978-1-5386-5479-8},
}