Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology

Dongjun Lee, Jaeduk Han. Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology. In 18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021. pages 292-293, IEEE, 2021. [doi]

Abstract

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