Table of Contents

• Analysis of Layout Arrangment for CMOS Oscillators to Reduce Overall Variation on WaferPang-Yen Lou, Yung-Yuan Ho, Chua-Chin Wang. 1-2 [doi]
• Early HW/SW Co-Verification Using Virtual PlatformsJungyun Choi, Kyungsu Kang, Byunghoon Lee, Sangho Park, Jae-Woo Im. 1-2 [doi]
• Mitigating IR-Drop with Design Technology Co-Optimization for Sub-Nanometer Node TechnologyDohyeon Lee, Heecheol Hwang, Hyunteck Oh, Yongchan James Ban. 1-2 [doi]
• Self-coupled MASH Delta-Sigma Modulator with Zero OptimizationJingying Zhang, Yang Zhao, Mingyi Chen, Chixiao Chen, Fan Ye 0001, Liang Qi. 1-2 [doi]
• A Circular-based TSV Repair ArchitectureYoungkwang Lee, Donghyun Han, Sooryeong Lee, Sungho Kang. 1-2 [doi]
• Digital Calibration of 1.5 bits/stage Algorithmic ADCChinmaye Ramamurthy, Chetan D. Parikh, Subhajit Sen. 3-4 [doi]
• A Design of Low-Power Bootstrapped CMOS Switch for 20MS/s 12-bit Charge Sharing SAR ADCsJung-Hyun Lee, Kang-Yoon Lee. 5-6 [doi]
• A 0.6-V 400-KS/s Low Noise Asynchronous SAR ADC With Dual-Domain ComparisonSang-Hoon Lee, Won Young Lee. 7-8 [doi]
• Resistive Degeneration Linearization Dynamic Residue Amplifiers for Pipelined ADCsZiwei Li, Guoyao Wu, Yutong Zhao, Fan Ye 0001, Junyan Ren. 9-10 [doi]
• On-chip CMOS Corner Detector Design for Panel DriversPang-Yen Lou, Ying-Xuan Chen, Chua-Chin Wang. 11-12 [doi]
• Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUTHeping Yang, Hui Chen, Yuxiang Fu, Li Li 0003. 13-14 [doi]
• A Low-Complexity Architecture for Implementing Square to Tenth Root of Complex NumbersJin Xu, Lin Jiang, Hui Chen, Yuxiang Fu, Li Li 0003. 15-16 [doi]
• ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3Ronaldo Serrano, Ckristian Duran, Trong-Thuc Hoang, Marco Sarmiento, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham. 17-18 [doi]
• Efficient Partial Sum Architecture and Memory Reduction Method for SC-Flip Polar DecoderJae Hong Roh, Useok Lee, Yongje Lee, Myung Hoon Sunwoo. 19-20 [doi]
• Enhanced Depth Map Estimation in Low Light Conditions for RGB CamerasJoseph Chang, Truong Q. Nguyen. 21-22 [doi]
• Differential Gaze Estimation with Ocular Counter-Rolling CompensationShiwei Jin, Ji Dai, Truong Q. Nguyen. 23-24 [doi]
• Low-Complexity Voice Activity Detection Algorithm for Edge-Level DeviceJin Hyun, Seungsik Moon, Youngjoo Lee. 25-26 [doi]
• A Convolutional Neural Network Pipeline For Multi-Temporal Retinal Image RegistrationChi-Jui Ho, Yiqian Wang, Junkang Zhang, Truong Q. Nguyen, Cheolhong An. 27-28 [doi]
• Human-Inspired Camera: A Novel Camera System for Computer VisionShubham Kumar, Jonathan Mi, Qingyuan Zhang, Benjamin Chang, Hao Le, Ramsin Khoshabeh, Truong Nguyen 0001. 29-30 [doi]
• A 2-GHz Reconfigurable Transmitter Using A Class-D PA and A Multi-Tapped TransformerReza E. Rad, Soon Ho Choi, Sungjin Kim, Behnam Samadpoor Rikan, Kang-Yoon Lee. 31-32 [doi]
• Design of Multiplying Delay Locked Loop that prevents Harmonic Lock and is insensitive to PVT VariationHo Won Kim, Kang-Yoon Lee. 33-34 [doi]
• A Design of High Power SP7T and SP8T RF Switches using SOI CMOS TechnologyDavid Kim, Kang-Yoon Lee. 35-36 [doi]
• Design of 66.5dB IRR Baseband Analog with Filter TuningJi Hoon Song, Kang-Yoon Lee. 37-38 [doi]
• Wideband LC VCO with 39.3 % Frequency Tuning Range for Dielectric Spectroscopy SystemKiho Lee, Dong-Ho Lee, Jusung Kim, Songcheol Hong. 39-40 [doi]
• A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOSJun Feng, Mohammadreza Beikmirza, Mohammadreza Mehrpoo, Leo C. N. de Vreede, Morteza S. Alavi. 41-42 [doi]
• A 30-Gb/s PAM-8 Transmitter with a 2-Tap Feed-Forward Equalizer and Background Clock CalibrationSanghyeon Park, Jae-Nam Kim, Seung-Ah Park, Jung-Hoon Chun. 43-44 [doi]
• An 8 - 26 Gb/s Single Loop Reference-less CDR with Unrestricted Frequency AcquisitionHyung-Wook Lee, Kyeong-Min Ko, Jin-Ku Kang. 45-46 [doi]
• A Maximum Eye Tracking Clock-and-Data Recovery Scheme with Golden Section Search(GSS) Algorithm in 28-nm CMOSSeungha Roh, Moon-Chul Choi, Deog Kyoon Jeong. 47-48 [doi]
• A Stochastic Variable Gain Amplifier Adaptation for PAM-4 signalingMinkyo Shim, Woonghee Lee, Yunhee Lee, Deog Kyoon Jeong. 49-50 [doi]
• Impacts of HLS Optimizations on Side-Channel Leakage for AES CircuitsTakumi Mizuno, Qidi Zhang, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama. 53-54 [doi]
• Design of a 32-bit Accuracy-Controllable Approximate Multiplier for FPGAsMasaki Sano, Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Tongxin Yang, Tomoaki Ukezono. 55-56 [doi]
• Scheduling with Variable-Cycle Approximate Functional Units in High-Level SynthesisKoyu Ohata, Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama. 57-58 [doi]
• Comparative Analysis between Verilog and Chisel in RISC-V Core Design and VerificationJaekyung Im, Seokhyeong Kang. 59-60 [doi]
• A Self Synchronized-Switch Rectifier for Piezoelectric-Vibration Energy-Harvesting SystemsYong-Zheng Wang, Ching-Yuan Yang. 61-62 [doi]
• A Single-Inductor Triple-Source Energy Harvesting Interface for Batterty-Assisted IoT ApplicationsMing-Jie Chung, Chih-Lun Lo, Po-Hung Chen. 63-64 [doi]
• Asymmetric Charge Transfer Scheme Model in ML-SSHC with Consistent Power Extraction Improvement for Piezoelectric Energy HarvestersArcel G. Leynes, John Richard E. Hizon, Maria Theresa G. de Leon, Marc D. Rosales. 65-66 [doi]
• Precision Exploration of Floating-Point Arithmetic for Spiking Neural NetworksMyeongjin Kwak, Hyoju Seo, Yongtae Kim. 71-72 [doi]
• Binary/Ternary Vector Matrix Multiplier with 3T-2R CBRAM CellHwan-Jin Joo, Kee-Won Kwon. 73-74 [doi]
• Memcapacitor based Minimum and Maximum Gate DesignJiyoung Min, Sunmean Kim, Seokhyeong Kang. 75-76 [doi]
• Low Energy and Error Resilient SOT-MRAM based FPGA LUT CellDongsu Kim, Jongsun Park. 77-78 [doi]
• Digital LDO with reference-less adaptive CLK generation and bit-shifting Coarse-Fine-controlWooyoung Choi, Seung-Myeong Yu, Yunha Kang, Junyoung Song. 79-80 [doi]
• Novel In-memory Computing Circuit using Muller C-elementSoonbum Song, Youngmin Kim. 81-82 [doi]
• Pre-RTL DNN Hardware Evaluator With Fused Layer SupportChih-Chyau Yang, Tian-Sheuan Chang. 83-84 [doi]
• Continual Learning for Instance Segmentation to Mitigate Catastrophic ForgettingJeong Jun Lee, Seung-Il Lee, Hyun Kim. 85-86 [doi]
• Object Detection Network Robust to Local Illumination VariationsJinyeon Kim, Jonghee Park, Sang-Seol Lee, Sung-Joon Jang. 87-88 [doi]
• A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inferenceJoonhyung Kim, Jongsun Park. 89-90 [doi]
• RF-DC Converter Using Loss Compensation and Adaptive Matching NetworkKee Hoon Yang, Seob Oh, Jae Bin Kim, JongWan Jo, Kang-Yoon Lee. 93-94 [doi]
• A High Speed OOK Modulator at 300 GHz using LO Cancellation TechniqueZubair Mehmood, Munkyo Seo. 95-96 [doi]
• Design of 100 GHz OOK Transceiver in 28nm CMOS Process for High Speed CommunicationZubair Mehmood, Waseem Abbas, Munkyo Seo. 99-100 [doi]
• Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D ICDonghyun Han, Youngkwang Lee, Sooryeong Lee, Sungho Kang. 101-102 [doi]
• Short Word-Line Pulse with Fast Bit-Line Boosting For High Throughput 6T SRAM-based Compute In-memory DesignMinseo Kim, Jongsun Park. 103-104 [doi]
• Local Bit-line Charge-sharing based Pre-charging SRAM for Near Threshold Voltage OperationHyunchul Park, Jongsun Park. 105-106 [doi]
• A Time-Domain Computing-In-Memory Micro using Ring OscillatorYixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim. 107-108 [doi]
• Giga-sample Data Acquisition Method for High-speed DDR5 SDRAMSeunggyu Lee, Jongho Yoon, Jakang Lee, Seokhyeong Kang. 109-110 [doi]
• Optimized Method for Thermal Tracking in 3D NoC Systems by Using ANNMenghao Guo, Tong Cheng, Li Li, Yuxiang Fu. 111-112 [doi]
• A Fast Locking All Digital Delay Locked Loop with wide operating frequency ranged from 0.5 GHz to 1.8 GHz in 40nm ProcessKo-Chi Kuo. 113-114 [doi]
• A newton raphson method based approximate divider design for color quantization applicationK. J. N. S. Bhargav, Sairam Palisetti, Madhav Rao. 115-116 [doi]
• Data Protection Method for Flash Memory in Serial Peripheral InterfaceAeri Kim, Seokhyeong Kang. 117-118 [doi]
• Stochastic Edge Detection for Fine-Grained Progressive PrecisionYoungwook Lee, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi. 119-120 [doi]
• Second-order Noise Shaping SAR ADC using 3-input Comparator with Voltage Gain CalibrationHoyong Jung, Neungin Jeon, Young-Chan Jang. 123-124 [doi]
• 12-Bit 5 MS/s SAR ADC with Split Type DAC for BLEBehnam Samadpoor Rikan, Arash Hejazi, Daeyoung Choi, Reza E. Rad, YoungGun Pu, Kang-Yoon Lee. 125-126 [doi]
• A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOSHong-Seok Choi, Seungha Roh, SangHee Lee, Jung-hoon Park, Kwanghoon Lee, Young Ha Hwang, Deog Kyoon Jeong. 127-128 [doi]
• A High Linearity Bootstrapped Switch with Leakage Current Suppressed for GS/s Sampling Rate ADCJingchao Lan, Yan Zheng, Yimin Wu, Min Chen, Fan Ye 0001, Junyan Ren. 129-130 [doi]
• A CMOS Power Management Unit with Undervoltage Lockout Circuit as Startup for Piezoelectric Energy Harvesting ApplicationsSteven Lorenzo Mindoro, John Owen Cabuyadao, Arcel G. Leynes, Maria Sophia Ralota, Zyrel Renzo Sanchez, John Richard E. Hizon, Marc D. Rosales, Maria Theresa G. de Leon. 131-132 [doi]
• 12 V PZE Harvesting Circuit For AUV Using Boost Converter with Resistor Matching ControllerTzung-Je Lee, Yu-Wei Liu. 133-134 [doi]
• Adaptive ON - Time Boost Converter in 45nm for Solar Cell ApplicationsSunita M. S, Tejas Somashekhar, Shashidhar Tantry. 135-136 [doi]
• Two Stage CMOS Bio-medical Amplifier Based on a highly Linear TΩ Pseudo-ResistorIsraa Y. AbuShawish, Soliman A. Mahmoud. 143-144 [doi]
• Feed-Forward Control of PAM4 CTLE for Optical Receivers Based on a Step Response AnalysisYukinaga Shimoda, Kota Hayashi, Daisuke Ito, Makoto Nakamura. 145-146 [doi]
• Digitally Programmable Gain and Tunable Band-Width DPOTA based Bio-medical AmplifierIsraa Y. AbuShawish, Soliman A. Mahmoud. 147-148 [doi]
• Low Noise Analog Front End for IoT SensorJieun Park, Kang-Yoon Lee. 149-150 [doi]
• Ternary Sense Amplifier Design for Ternary SRAMMinjeong Choi, Youngchang Choi, Sunmean Kim, Seokhyeong Kang. 151-152 [doi]
• Design of an Accuracy Enhanced Imprecise Adder with Half Adder-based ApproximationHyoju Seo, Jungwon Lee, Hyelin Seok, Yongtae Kim. 153-154 [doi]
• A 20-Gb/s Digitally Adaptive Linear Equalizer with 25dB loss for Single-ended Interfaces in 65nm CMOSYunha Kang, Junyoung Song. 155-156 [doi]
• A Voltage-Controlled Magnetic Anisotropy based True Random Number GeneratorLawrence Roman A. Quizon, Anastacia B. Alvarez, Christoper G. Santos, Marc D. Rosales, John Richard E. Hizon, Maria Patricia Rouelli G. Sabino. 159-160 [doi]
• Triple-Rail Stochastic Number and Its ApplicationsShoki Kawaminami, Shigeru Yamashita. 161-162 [doi]
• Analyses of Power Staple Inserting Methodologies for Mitigating IR-DropsJaejoon Yoon, Sehyeon Chung, Taewhan Kim. 169-170 [doi]
• Power Integrity Specification Definition for an Integrated Clock Circuit DesignFern Nee Tan, Mohamad Shahrir Tamrin, Jia Yun Chuah. 171-172 [doi]
• PSO-based Design Procedure for Class-DE InverterWenqi Zhu, Yutaro Komiyama, Kien Nguyan, Hiroo Sekiya. 173-174 [doi]
• Load-Independent Inverse Class-E Oscillator with Armstrong-Oscillator Based TopologyYutaro Komiyama, Shuya Matsuhashi, Wenqi Zhu, Kien Nguyen, Hiroo Sekiya. 175-176 [doi]
• An Estimation Method for Controlling Unstable Periodic Orbit Without Using Poincaré MapSatoshi Aoki, Takuji Kousaka, Shota Uchino, Daiki Hozumi, Hiroyuki Asahara. 177-178 [doi]
• Ability to generate output series for Hysteresis Reservoir ComputingTsukasa Saito, Kenya Jin'no. 179-180 [doi]
• Information Transmission Focusing on Complex Networks Consisting of OscillatorsTsuyoshi Isozaki, Yoko Uwate, Yoshifumi Nishio. 181-182 [doi]
• Suppression of Chaos Propagation in Ladder Chaotic Circuits by Local Switching of Coupling StrengthNaoto Yonemoto, Yoko Uwate, Yoshifumi Nishio. 183-184 [doi]
• Real-Time Characteristics Identification for Partial Shaded Photovoltaic StringsDou Hong, Jieming Ma, Ka Lok Man, Huiqing Wen, Prudence W. H. Wong. 185-186 [doi]
• Artificial synaptic behavior and its improvement of RRAM device with stacked solution-processed MXene layersZong Jie Shen, Chun Zhao, Yina Liu, Li Yang, Cezhou Zhao. 187-188 [doi]
• Power Consumption Analysis of a Fractional Approach to BANs Time SynchronizationGianfranco Avitabile, Ka Lok Man, Antonello Florio. 189-190 [doi]
• Design on Smart Grid and Irrigation Management: based on Information SharingSanghyuk Lee, Youpeng Yang, Mohamed AbdelAzim Ibrahim, ChangHyun Jun, Eng Gee Lim, Yujia Zhai. 191-192 [doi]
• A Linear Array Mutual Coupling Compensation Technique for Angle of Arrival EstimationAntonello Florio, Gianfranco Avitabile. 193-194 [doi]
• Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge DevicesTianzhu Xiong, Yongliang Zhou, Yuyao Kong, Bo Wang, An Guo, Yufei Wang, Chen Xue, Haiming Hsu, Xin Si, Jun Yang. 195-196 [doi]
• Challenges and Opportunities of Energy-Efficient CIM SoC Design for Edge AI DevicesJinshan Yue, Wenyu Sun, Huazhong Yang, Yongpan Liu. 197-198 [doi]
• Soft Error Sensitivity of Magnetic Random Access Memory and Its Radiation Hardening DesignBi Wang, Zhaohao Wang, Min Wang, Weisheng Zhao, Liang Wang, Yuanfu Zhao. 199-200 [doi]
• A Survey on Feature Point Extraction TechniquesKun Huang, Jingyuan Li, Ye Liu, Liang Chang, Jun Zhou. 201-202 [doi]
• Safety Verification of AMS Circuits with Piecewise-Linear System Reachability AnalysisSeyoung Kim, Heechun Park, Jaeha Kim. 203-206 [doi]
• Fast Automatic Circuit Optimization Using Deep LearningJiwoo Hong, Sunghoon Kim, Jaeha Kim, Dongsuk Jeon. 207-210 [doi]
• Reducing Refresh Overhead with In-DRAM Error Correction CodesHanbyeol Kwon, Kwangrae Kim, Dongsuk Jeon, Ki-Seok Chung. 211-214 [doi]
• Challenges on DTCO Methodology Towards Deep Submicron Interconnect TechnologyHeechun Park, Kyungjoon Chang, Jooyeon Jeong, Jaehoon Ahn, Ki-Seok Chung, Taewhan Kim. 215-218 [doi]
• Local and Global Activities of Izhikevich Neuron Model in NetworksYoko Uwate, Yoshifumi Nishio, Marie Engelene J. Obien, Urs Frey. 219-220 [doi]
• Memristor Crossbar Circuits for Neuromorphic pattern RecognitionMinh Le, Son Ngoc Truong. 221-222 [doi]
• Trend of Emerging Non-Volatile Memory for AI ProcessorLiang Chang 0002, Chenglong Li, Xin Zhao, Zixuan Zhu, Yi Tong, Shuisheng Lin, Jun Zhou 0017. 223-224 [doi]
• Body-coupled wireless power transfer and energy harvesting for wearablesJerald Yoo. 225 [doi]
• Trends of Modern Processors for AI AccelerationKyuHo Lee. 227 [doi]
• EdgeRL: A Light-Weight C/C++ Framework for On-Device Reinforcement LearningSang-Soo Park, Dong-Hee Kim, Jun-Gu Kang, Ki-Seok Chung. 235-236 [doi]
• Implementation of Optimal CNN Accelerators for Mobile Devices: Algorithm, Architecture, and Memory System Co-DesignHyun Kim. 237-238 [doi]
• Memory-Centric Architecture of Neural Processing Unit for Edge DeviceEunchong Lee, Minyong Sung, Sung-Joon Jang, Jonghee Park, Sang-Seol Lee. 240-241 [doi]
• A Digitally Controlled Analog kernel for Convolutional Neural NetworksMalik Summair Asghar, Muhammad Junaid, HyungWon Kim 0001, Saad Arslan, Syed Asmat Ali Shah. 242-243 [doi]
• Power-efficient VCO-based ADCs for Wireless Communication SystemsXinpeng Xing, Xueqian Shang, Senji Liu, Xinfa Zheng, Georges G. E. Gielen. 244-245 [doi]
• Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and CalibrationDanfeng Zhai, Chixiao Chen, Liang Qi, Fan Ye 0001, Junyan Ren. 246-247 [doi]
• Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCsMingqiang Guo, Sai-Weng Sin, Rui Paulo Martins. 248-249 [doi]
• High speed Continuous-time Delta Sigma Modulators for Wide-band Applications: A review paperAnkesh Jain. 250-251 [doi]
• Continuous-time Delta-Sigma Modulators: Single-loop versus MASHLiang Qi, Tianming Ni, Xinyu Qin, Mingyi Chen, Yongfu Li, Guoxing Wang. 252-253 [doi]
• High-accuracy and Low-latency Hybrid Stochastic Computing for Artificial Neural NetworkKun-Chih Jimmy Chen, Cheng-Ting Chen. 254-255 [doi]
• LSMQ: A Layer-Wise Sensitivity-Based Mixed-Precision Quantization Method for Bit-Flexible CNN AcceleratorYimin Huang, Kai Chen, Zhuang Shao, Yichuan Bai, Yafeng Huang, Yuan Du, Li Du, Zhongfeng Wang. 256-257 [doi]
• CTT-based Non-Volatile Deep Neural Network Accelerator DesignYang Xiao, Wuyu Fan, Yuan Du, Li Du, Mau-Chung Frank Chang. 258-259 [doi]
• An Energy-Efficient Ring-Based CIM Accelerator using High-Linearity eNVM for Deep Neural NetworksPo-Tsang Huang, Ting-Wei Liu, Wei Lu, Yu-Hsien Lin, Wei Hwang. 260-261 [doi]
• On Reconfiguring Memory-Centric AI Edge Devices for CIMHung-Ming Chen, Cheng-En Ni, Kang-Yu Chang, Tzu-Chieh Chiang, Shih-Han Chang, Cheng-Yu Chiang, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou. 262-263 [doi]
• Spatial Non-Maximum Suppression for Object Detection using Correlation and Dynamic ThresholdsXiangyu Zhang, Wenyan Su, Juan Li, Jingwei Li, Xin Lou. 264-265 [doi]
• Radar Based Real-Time Fall Detection System with Low Power ConsumptionJincheng Lu, Zixuan Ou, Ziyu Liu, Cheng Han, Wenbin Ye. 266-267 [doi]
• Detecting LED Chip Surface Defects with Modified Faster R-CNNZhiwen Zhang, Qian Gong, Yuan Cao, Cheng Yin, Enyi Yao, Yanhua Liu, Yongqing Pan. 268-269 [doi]
• Application on Demodulation of FBG Sensing Signals using Phase Detection Algorithm of Intake and ExhaustChenjie Kong, Tianming Chen, Jun Zhang, Guizhong Jiang, Yuan Shen, Pan He. 270-271 [doi]
• A Review on Recent Development of Input Impedance Boosting for Bio-Potential AmplifiersShuang Song, Yizhao Zhou, Mengyu Li, Menglian Zhao. 272-273 [doi]
• RRAM-Based STDP Network for Edge Computing in Wearable/Implantable DevicesYukai Shen, Shiwei Wang, Carolina Mora Lopez. 274-275 [doi]
• PPG Sensors for The New Normal: A ReviewQiuyang Lin, Nick Van Helleptte. 276-277 [doi]
• High-speed EEG-Based Brain-Computer Interface with Wide Dynamic-range ADCMing Gu, Fang Yuan, Jun Yan, Mingyi Chen. 278-279 [doi]
• Implement Tunable Sub-TΩ On-chip Resistor for Vital Signal Acquisition: A ReviewMingyi Chen, Yuzhi Hao, Liang Qi, Yongfu Li, Jun Yan. 280-281 [doi]
• Hybrid Dynamic Fixed Point Quantization Methodology for AI AcceleratorsWei-Hung Lin, Hsu-Yu Kao, Shih-Hsu Huang. 282-283 [doi]
• Reinforcement Learning for Runtime Optimization for High Performance and Energy Efficient NoCMd Farhadur Reza. 284-285 [doi]
• LSTM-based Temperature Prediction and Hotspot Tracking for Thermal-aware 3D NoC SystemTong Cheng, Haoyu Du, Li Li, Yuxiang Fu. 286-287 [doi]
• Solving Traveling Salesman Problems Using Ising Models with Simulated BifurcationTingting Zhang, Qichao Tao, Jie Han 0001. 288-289 [doi]
• A Reconfigurable Accelerator Design for Quantized Depthwise Separable ConvolutionsYu-Guang Chen, Hung Yi Chiang, Chi-Wei Hsu, Tsung-Han Hsieh, Jing-Yang Jou. 290-291 [doi]
• Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS TechnologyDongjun Lee, Jaeduk Han. 292-293 [doi]
• A Constant On-Time Buck Converter with Fully Integrated Average Current Sensing SchemeInho Jeon, Kyounghyun Min, Jinwoo Park, Jeongjin Roh, Deok-Ju Moon, Hyoung-rae Kim. 294-295 [doi]
• Wideband Operational Trans-Conductance Amplifier with Feed-Forward Compensation TechniqueMuhammad Fakhri Mauludin, Dong-Ho Lee, Jusung Kim. 298-299 [doi]
• A 0.2 ‒ 1.2GHz Adaptive Bandwidth PLL with Controllable KVCOChangmin Song, Se-Hyeon Cho, Young-Chan Jang. 300-301 [doi]
• A 5.8 GHz RF-DC Based Energy-Harvesting Front-End with a Load-Lighting LC-Oscillator Based Voltage Booster for a SWIPT ICReza E. Rad, Behnam Samadpoor Rikan, Kang-Yoon Lee. 307-308 [doi]
• A 7.68 GHz Fast-Lock Low-Jitter Digital MDLLJunghoon Jin, Seungjun Kim, Sunguk Choi, Pil-Ho Lee, Sang Jae Rhee, Ki-hwan Choi, Jongsun Kim. 311-312 [doi]
• A High-speed Wireless Data Transfer for Non - Destructive TestingHanh Dangba, Thang Bui-ngoc, Hae-Jin Kim, Jun-hee Song, Chaiyoon Chung, Gyung-Su Byun. 315-316 [doi]
• High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic CircuitDong Han Ko, Sehee Lim, Young Kyu Lee, Seong-Ook Jung. 321-322 [doi]
• A Low-Power Low-Noise Neural Signal Acquisition Amplifier with Tolerance to Large Stimulation ArtifactsDonghoon Choi, Hyouk-Kyu Cha. 325-326 [doi]
• CAN Data Compression Based on Sorting and Mapping MethodShiyi Jin, Yeonjin Kim, Jin-Gyun Chung, Yongen Kim. 327-328 [doi]
• Digital Controller Implementation of Grid-Tied Zeta Inverter Using 16-bits MicrocontrollerWoo-Young Choi. 329-330 [doi]
• Two-step Time-to-Digital Converter using pulse-shifting time-difference repetition circuitChang han Rho, Jin-Ku Kang, Jin Liu. 333-334 [doi]
• A SCAN Chain Generator for Verification of Full-Custom Integrated CircuitsTae-ho Shin, Jaeduk Han. 335-336 [doi]
• Low Power Gate Diffusion Input Full Adder using Floating BodyGeuntae Park, Youngmin Kim. 337-338 [doi]
• Efficient Power Control Using Variable Resolution Algorithm for LiDAR Sensor-based Autonomous VehicleSanghoon Lee, Daejin Park. 341-342 [doi]
• A simplified, high-speed, Error-tolerant Adder using Zero Padding MethodDongchan Lee, Youngmin Kim. 343-344 [doi]
• Configurable Butterfly Unit Architecture for NTT/INTT in Homomorphic EncryptionPhap Duong-Ngoc, Tuy Nguyen Tan, Hanho Lee. 345-346 [doi]
• Low Power High Performance Match Line Design of Content Addressable MemoryHyunju Kim, Hyungtak Kim, Youngmin Kim. 347-348 [doi]
• Efficient Signal Processing Acceleration using OpenCL-based FPGA-GPU Hybrid Cooperation for Reconfigurable ECG DiagnosisDongkyu Lee, Seungmin Lee, Daejin Park. 349-350 [doi]
• FPGA-based Scalable Road Image Stochastic Denosing ApproachCheolhyeong Park, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi. 351-352 [doi]
• 2β-softmax: A Hardware-Friendly Activation Function with Low Complexity and High PerformanceYonggang Zhang, Hui Chen, Yuxiang Fu, Li Li 0003. 353-354 [doi]
• Design of emotion recognition system using neuromorphic computing techniqueB. S. Ajay, Madhav Rao. 355-356 [doi]
• Layer-wise Pruning of Transformer Attention Heads for Efficient Language ModelingKyuhong Shim, Iksoo Choi, Wonyong Sung, Jungwook Choi. 357-358 [doi]
• CNN encryption using XOR Gate for Hardware OptimizationKi-Beom Lee, Sumin Lee, Sunghwan Joo, Hong Keun Ahn, Young Seok Jung, Seong-Ook Jung. 359-360 [doi]
• Intrinsic Capacitance based Multi bit Computing in MemoryYoung Kyu Lee, Minjune Yeo, Seokhee Cho, Seong-Ook Jung. 361-362 [doi]
• Components Analysis on Audio Signal MixturesChanhee Lee, Sangho Yoon, Seokhyeong Kang. 363-364 [doi]
• Hybrid Test Access Mechanism for Multiple Identical CoresSangjun Lee, Jongho Park, Inhwan Lee, Kwonhyoung Lee, Sungho Kang. 365-366 [doi]
• Power Side-Channel Analysis for Different Adders on FPGAYilin Zhao, Qidi Zhang, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama. 367-368 [doi]
• High-Level Synthesis of Approximate Computing Circuits with Dual Accuracy ModesKenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama. 369-370 [doi]
• ASIC Implementation of Magnetic Induction based Wireless Communication SystemJaehyuk So, Dong-hyun Lee, Min-Joon Kim, Yeon-Kug Moon. 371-372 [doi]
• FPGA Design Duplication based on the Bitstream ExtractionSoyeon Choi, Nari Im, Hoyoung Yoo. 373-374 [doi]
• A Low-Power Low-Area SoC based in RISC-V Processor for IoT ApplicationsRonaldo Serrano, Marco Sarmiento, Ckristian Duran, Khai-Duy Nguyen, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham. 375-376 [doi]
• High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS TechnologyGaeryun Sung, Jaeduk Han. 377-378 [doi]
• A Sequential Two-step Algorithm For DC Offset Cancellation of PAM-4 ReceiverYunhee Lee, Woonghee Lee, Minkyo Shim, Deog Kyoon Jeong. 379-380 [doi]
• Auto-tracking Method with Optimal Reference Voltage for PAM-4 ReceiverDaeho Yun, Deog Kyoon Jeong. 381-382 [doi]
• A SAR ADC with Segment Binary Weighted Attenuation Capacitor DAC layout techniqueKeun-Yong Chung, Kwang-Hyun Baek, Bo-Kyong Choi. 389-390 [doi]
• K-means Clustering-specific Lightweight RISC-V processorWooyoung Lee, Jina Park, Changjun Byun, Eunjin Choi, Jae-Hyoung Lee, Woojoo Lee, Kyung Jin Byun, Kyuseung Han. 391-392 [doi]
• Low-Complexity On-Device ECG Classifier using Binarized Neural NetworkSunwoo Yoo, Seungwoo Hong, Youngjoo Lee. 393-394 [doi]
• An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs)Eun-Bin Park, Taigon Song. 395-396 [doi]
• A Haar Classifier Accelerator with Reduced Multiplexer UsageSanghyun Lee, Byungin Moon. 399-400 [doi]
• Haar Filter Hardware Architecture for the Accuracy Improvement of Stereo Vision SystemsCheol Ho Choi, Younghyeon Kim, Jiseok Ha, Byungin Moon. 401-402 [doi]
• Novel Performance Evaluation Approach of AMBA AXI-Based SoC DesignTuy Nguyen Tan, Phap Duong-Ngoc, Thang Xuan Pham, Hanho Lee. 403-404 [doi]
• Design of 20Gb/s PAM4 Transmitter with Maximum Transition Elimination and Transition Compensation TechniquesKyeong-Min Ko, Dohyeon Kwon, Jin-Ku Kang. 405-406 [doi]
• A Gain Boosted Single-Ended 300 GHz InP HBT Oscillator for Terahertz ApplicationsWaseem Abbas, Munkyo Seo. 407-408 [doi]
• A Non-linear Input Converter Inversely Pre-distorted Against Nonlinear Behavior of FG-based Neuromorphic Synaptic DevicesJin-Young Hwang, Kee-Won Kwon. 409-410 [doi]
• CNN Accelerator with Minimal On-Chip Memory Based on Hierarchical ArrayHyun-Wook Son, YongSeok Na, Taehyun Kim, Ali A. Al-Hamid, Hyungwon Kim. 411-412 [doi]
• Understanding and Reducing Weight-Load Overhead of Systolic Deep Learning AcceleratorsJinwon Joo, Minyong Yoon, Jungwook Choi, Mingu Kang, JongGeon Lee, Jinin So, IlKwon Yun, Yongsuk Kwon, Kyungsoo Kim. 413-414 [doi]
• Hardware-friendly Log-scale Quantization for CNNs with Activation Functions Containing Negative ValuesDahun Choi, Hyun Kim. 415-416 [doi]
• Implementation of CNN based Demosaicking on FPGAJoon Hyeon Park, Min-Cheol Kim, Byeong Dae Lee, Myung Hoon Sunwoo. 417-418 [doi]
• LightNet: A Lightweight Neural Network for Image ClassificationAkshay Kumar Sharma, Byungho Kang, Kyung Ki Kim. 419-420 [doi]
• A Multi-Bit In-Memory-Computing SRAM Macro Using Column-Wise Charge Redistribution for DNN Inference in Edge Computing DevicesChangseon Chae, Subin Kim, Jonghang Choi, Jun-Eun Park. 421-422 [doi]
• Fusion for Tile-based Deconvolution LayersMin-Wu Jeong, Chae-Eun Rhee. 423-424 [doi]
• Secure Scan Design through Pseudo Fault InjectionSeokjun Jang, Hyungil Woo, Sunghoon Kim, Sungho Kang. 425-426 [doi]
• Post-bond Repair of Line Faults with Double-bit ECC for 3D MemoryYounwoo Yoo, Hayoung Lee, Seung-Ho Shin, Sungho Kang. 427-428 [doi]
• An Effective Spare Allocation Methodology for 3D Memory Repair with BIRASeung-Ho Shin, Hayoung Lee, Younwoo Yoo, Sungho Kang. 429-430 [doi]
• Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare StructureYoungki Moon, Hyunho Yoo, Donghyun Han, Sungho Kang. 431-432 [doi]