The following publications are possibly variants of this publication:
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- The design of high holding voltage SCR for whole-chip ESD protectionYong-Seo Koo, Kwang-Yeob Lee, Kui-Dong Kim, Jong-Ki Kwon. ieiceee, 5(17):624-630, 2008. [doi]
- 2-stage ESD protection circuit with high holding voltage and low trigger voltage for high voltage applicationsByung-Seok Lee, Hee-Guk Chae, Yong-Seo Koo, Kyeong-Il Do, Jin-Woo Eo. elinfocom 2019: 1-4 [doi]