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Pil-Ho Lee, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang. An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock. IEEE Trans. VLSI Syst., 25(4):1386-1396, 2017. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity AnalysisPil-Ho Lee, Yu-Jeong Hwang, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang. ieicet, 99-C(4):440-443, 2016. [doi] A chip-to-chip clock-deskewing circuit for 3-D ICsAi-Jia Chuang, Yu Lee, Ching-Yuan Yang. iscas 2012: 1652-1655 [doi]
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