Jaejun Lee, Sungho Lee, Joontae Park, Sangwook Nam. Architecture of a multi-slot main memory system for 3.2 Gbps operation. In International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France. pages 3857-3860, IEEE, 2010. [doi]
Abstract is missing.