Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units

Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano. Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. IPSJ T. on System LSI Design Methodology, 4:182-192, 2011. [doi]

@article{LeiIUNKNA11,
  title = {Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units},
  author = {Zhao Lei and Daisuke Ikebuchi and Kimiyoshi Usami and Mitaro Namiki and Masaaki Kondo and Hiroshi Nakamura and Hideharu Amano},
  year = {2011},
  doi = {10.2197/ipsjtsldm.4.182},
  url = {http://dx.doi.org/10.2197/ipsjtsldm.4.182},
  researchr = {https://researchr.org/publication/LeiIUNKNA11},
  cites = {0},
  citedby = {0},
  journal = {IPSJ T. on System LSI Design Methodology},
  volume = {4},
  pages = {182-192},
}