The following publications are possibly variants of this publication:
- A highly parallel Turbo Product Code decoder without interleaving resourceCamille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel, Deepak Gupta. sips 2008: 1-6 [doi]
- From Parallelism Levels to a Multi-ASIP Architecture for Turbo DecodingOlivier Muller, Amer Baghdadi, Michel Jézéquel. tvlsi, 17(1):92-102, 2009. [doi]
- New architecture for high data rate turbo decoding of product codesJavier Cuevas, Patrick Adde, Sylvie Kerouédan, Ramesh Pyndiah. globecom 2002: 1363-1367 [doi]
- High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA PrototypingCamille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel. vlsisp, 57(3):349-361, 2009. [doi]