Weiguo Li, Zhipeng Huang 0009, Bei Yu 0001, Wenxing Zhu, Xingquan Li. Toward Controllable Hierarchical Clock Tree Synthesis with Skew-Latency-Load Tree. In Vivek De, editor, Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024. ACM, 2024. [doi]
Abstract is missing.