Aizup-a pipelined processor design and implementation on XILINX FPGA chip - researchr publication

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Yamin Li, Wanming Chu. Aizup-a pipelined processor design and implementation on XILINX FPGA chip. In 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), Napa Valley, CA, USA, April 17-19, 1996. pages 98-106, IEEE, 1996. [doi]

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