Compact modeling of on-chip ESD protection devices using Verilog-A

Junjun Li, S. Joshi, R. Barnes, E. Rosenbaum. Compact modeling of on-chip ESD protection devices using Verilog-A. IEEE Trans. on CAD of Integrated Circuits and Systems, 25(6):1047-1063, 2006. [doi]

Abstract

Abstract is missing.