Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi. Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations. IEEE Trans. on CAD of Integrated Circuits and Systems, 27(6):1041-1054, 2008. [doi]
@article{LiLCP08,
title = {Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations},
author = {Xin Li and Jiayong Le and Mustafa Celik and Lawrence T. Pileggi},
year = {2008},
doi = {10.1109/TCAD.2008.923241},
url = {http://dx.doi.org/10.1109/TCAD.2008.923241},
tags = {logic},
researchr = {https://researchr.org/publication/LiLCP08},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {27},
number = {6},
pages = {1041-1054},
}