Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations - researchr publication

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Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi. Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations. IEEE Trans. on CAD of Integrated Circuits and Systems, 27(6):1041-1054, 2008. [doi]

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