Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology - researchr publication authors

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Lixiang Li, Yuanqing Li, Haibin Wang, Rui Liu, Qiong Wu, Michael Newton, Yuan Ma, Li Chen. Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology. J. Electronic Testing, 31(5-6):561-568, 2015. [doi]

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