Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology

Lixiang Li, Yuanqing Li, Haibin Wang, Rui Liu, Qiong Wu, Michael Newton, Yuan Ma, Li Chen. Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology. J. Electronic Testing, 31(5-6):561-568, 2015. [doi]

@article{LiLWLWNMC15,
  title = {Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology},
  author = {Lixiang Li and Yuanqing Li and Haibin Wang and Rui Liu and Qiong Wu and Michael Newton and Yuan Ma and Li Chen},
  year = {2015},
  doi = {10.1007/s10836-015-5549-x},
  url = {http://dx.doi.org/10.1007/s10836-015-5549-x},
  researchr = {https://researchr.org/publication/LiLWLWNMC15},
  cites = {0},
  citedby = {0},
  journal = {J. Electronic Testing},
  volume = {31},
  number = {5-6},
  pages = {561-568},
}